1. Field of the Invention
The present invention relates to the field of translation look-a-side buffers, and, more particularly, it relates to the ability to translate a given input address to a user specified address location.
2. Description of the Related Art
A standard translation look-a-side buffer of the prior art enables a user to transfer an address request from a central processing unit (CPU) to an alternative address location in the system memory. The basic operation of a translation look-a-side buffer entails comparing an input address to a stored address to verify if the two addresses match each other. If no match has occurred, the input address is transferred through the buffer and is output to the system bus without modification. If a match occurs, the input address is replaced with a stored output address which is transferred to the system bus to replace the input address.
The operation of translation look-a-side buffers of the prior art is limited to a direct translation of an input memory location to a specified output memory location. The translation look-a-side buffer must compare the entire input address with the entire stored address in order to determine if an address translation is to occur. In addition, the translation look-a-side buffer must replace the entire input address with a new output address. These two requirements have greatly limited the number of possible applications of the translation look-a-side buffer. The look-a-side buffer is only useful in those applications where it is desirable to directly translate one address location to a new address location.
In order to provide improved memory system optimization, a need exists for a more flexible memory translation circuit that masks out certain bits from the input address which may be irrelevant to the comparison with the stored address before determining if the address translation is to occur. In addition, it is desirable to isolate certain portions of the input address that remain unchanged when the address translation occurs.